The present invention relates to a field of memory device comprising semiconductor integrated circuits. Specifically, the present invention relates to a boosting power circuit required for driving the memory device.
Regarding a dynamic memory device, as a method for having access to data of memory devices (memory cells) arranged in a matrix form, a potential is applied to word lines and data is exchanged between bit lines and the memory cells so as to perform reading and writing operations.
FIG. 12 shows memory cell arrays, a sense amplifier, and bit line precharge circuits of a typical dynamic random access memory (DRAM).
Reference numeral 111 denotes the memory cell arrays, reference numeral 112 denotes a bit line pair, reference numeral 113 denotes word lines, reference numeral 114 denotes bit line precharge circuits, reference numeral 115 denotes a sense amplifier, and reference numeral 116 denotes shared gates.
In the memory cell array 111, as for a single memory cell capacitor Co, the memory cell capacitor Co is connected to the source of an access transistor TWL, the bit line 112 is connected to the drain of the access transistor TWL, and the word line 113 is connected to the gate of the access transistor TWL.
The DRAM stores data by accumulating electric charge in the memory cell capacitor Co. A DRAM operating source voltage has been reduced while the DRAM has higher density and larger capacity.
In order to sufficiently secure accumulated electric charge in the memory cell capacitor Co in response to lower source voltage, a method has been generally used for applying a source potential VDD to the memory cell capacitor Co at H level and applying a GND potential thereto at L level. Therefore, as a gate potential of the access transistor TWL for transferring accumulated electric charge to the memory cell capacitor Co, a boosted potential (VPP) is necessary, which is higher in potential than the DRAM source voltage. In order to obtain the potential, assuming that the DRAM source voltage is VDD and the transistor TWL has a threshold voltage of VT, VPP=VDD+VT has to be satisfied.
Further, upon pre-charging the bit lines in response to lower source voltage VDD, in order to complete the pre-charging operation at high speed to increase a potential of the bit lines to a bit-line pre-charging potential VBP (=VDD/2), H level of a control signal of the bit line precharge circuit 114 is set at a boosted potential VPP.
Moreover, as shown in FIG. 12, the memory cell arrays (111(L), 111(R)) on the both sides of the sense amplifier 115 share the sense amplifier 115. This configuration has been generally adopted to reduce a layout area. Regarding the shared gates 116 as well used for realizing the above configuration, a boosted potential VPP is set as H level of a gate voltage to accurately transfer data at high speed between the memory cell arrays 111 and the sense amplifier 115.
As described above, in order to perform high-speed reading and writing operations in the DRAM in a stable manner, in addition to the source voltage VDD, a boosted power source VPP is necessary, which is set higher in potential than the source voltage. As a method for realizing such a voltage VPP, a boosting circuit having a charge pump circuit and so on therein is provided and the source voltage VDD is boosted to a high source potential VPP so as to obtain a high source potential.
FIG. 13 shows a conventional boosting power circuit.
Reference numeral 117 denotes a boosting circuit, reference numeral 118 denotes an auxiliary boosting circuit, reference numeral 119 denotes a timing control circuit, reference numeral 120 denotes an oscillator, reference numeral 121 denotes a detection circuit, and reference numeral 122 denotes an overboosting preventing circuit.
The boosting circuit 117 and the auxiliary boosting circuit 118 are realized by charge pump circuits which perform a boosting operation by transferring electric charge. Also, the outputs of the boosting circuit 117 and the auxiliary boosting circuit 118 are connected in parallel with each other.
The auxiliary boosting circuit 118 is provided for securing a boosted source potential VPP when a memory is in a standby status, which is achieved by setting its capability of supplying electric charge lower than that of the boosting circuit 117 so as to suppress consumption of current.
The boosting circuit 117 operates in synchronization with an internal memory activation signal IRAS when the memory is activated. Meanwhile, the auxiliary boosting circuit 118 operates asynchronously to the activation of the memory due to self-induced oscillation of the oscillator 120, based on a result detected by the detection circuit 121 on a boosted source potential VPP.
The overboosting preventing circuit 122 is provided for preventing a temporary overboosting of a boosted voltage VPP particularly when a source voltage VDD is high. The overboosting preventing circuit 122 makes it possible to prevent damage on an element of the device and to obtain reliability.
Here, FIG. 14 shows a schematic timing chart of the operation of the DRAM.
In FIG. 14, reference character CLK denotes a clock input signal, reference character RAS denotes a row address strobe input signal, reference character CAS denotes a column address strobe input signal, and reference character WE denotes a writing permission input signal.
In an example shown by FIG. 14, a reading cycle and a writing cycle are carried out in three clock periods. Pre-charging the bit lines is suspended substantially at the same time when the internal memory activation signal IRAS rises so as to determine a row address. And then, the word line corresponding to the selected row address is activated.
The word line is activated, so that electric charge accumulated in the memory cell capacitor is transferred to the bit line and a potential of the bit line is increased by a voltage value smaller than the bit line precharge potential VBP (=VDD/2) when H data is read. A potential of the bit line decreases by a voltage value smaller than the bit line precharge potential VBP when L data is read. In such a variation in potential of the bit line, a potential of the bit line is amplified to VDD at H level and to 0V at L level when the sense amplifier driving signal SE is set at H level.
The IRAS falls at a rising edge of the third clock, the word line is deactivated, and the sense amplifier driving signal SE is set at L level. Thereafter, a pre-charging operation for the bit line begins so as to precharge the bit line to the VBP. A series of operations are completed at this moment.
As indicated by circles in FIG. 14, the timings of consuming the boosted potential VPP generated in the boosting power circuit conform to the timing of activating the word line and the timing of operating a bit line precharge signal and the shared gates. This signal is substantially in synchronization with a rising edge and a falling edge of the internal memory activation signal IRAS.
In response to the above consumption of a boosted potential, as for the operation of the boosting circuit, it is possible to adopt two operating timings including performing a boosting operation only at a rising edge of the internal memory activation signal IRAS and performing a boosting operation at both of rising and falling edges of the IRAS.
As described above, as a timing of operating the boosting power circuit when the memory is in an activated status, it is possible to adopt two timings including operating in synchronization with a rising edge of the internal memory activation signal IRAS and operating both at rising and falling edges of the IRAS.
In a circuit using the former operating timing, boosted potentials conform to each other at a timing of activating the word lines. Meanwhile, electric charge is not supplied to the VPP by the boosting circuit upon precharging the bit line and activating the shared gates. Thus, an operating margin of the memory may be reduced due to a reduction in boosted potential.
Meanwhile, in a circuit using the latter boosting timing, the higher operating frequency of the memory, it is more difficult to obtain time required for boosting, resulting in an insufficient amount of transferred electric charge. Consequently, the operating efficiency of the boosting circuit is deteriorated.
A memory capacity and an operating speed of the DRAM both have been increased in response to a semiconductor circuit whose pattern has been finer in recent years. Hence, the conventional configuration is disadvantageous in stabilizing and smoothing boosted voltage and ensuring boosting capability.
Further, in response to a larger memory capacity resulted from a recent finer DRAM with higher density, gates requiring boosted power source increase in number. For this reason, capability of the boosted power source is demanded. Moreover, an operating speed of the memory is also inclined to increase. Therefore, in the boosting power circuit with the conventional configuration having a single charge pump circuit, the following problem may become obvious: a boosting operation cannot catch up with a consuming speed of the boosted power source, thereby deteriorating efficiency of the boosting circuit.
In response to variation in boosted source voltage that is caused by an increase in consumption, for example, it is possible to increase a smoothing capacitor. However, this solution increases a chip size so as to be disadvantageous in cost.
Consequently, the boosting power circuit with the conventional configuration has the following problems.
(1) Timings of operating the boosting circuit and consuming boosted voltage do not conform to each other and the timings are not appropriate, so that variation in voltage may be larger and an operating margin may be reduced.
(2) While a capacity of the memory is increased with higher speed, electric charge to be transferred for boosting increases. Thus, it is difficult to speed up the boosting operation with a single charge pump circuit, so that the boosting circuit has to operate at low boosting efficiency. Under some circumstances, a target boosted voltage value may not be achieved.
An object of the present invention is to provide a semiconductor integrated circuit including a new boosting power circuit, which is devised to solve a disadvantage of a boosting power circuit included in a conventional semiconductor integrated circuit.
According to the semiconductor integrated circuit of the present invention, a plurality of main charge pump circuits perform a boosting operation, which has been conventionally performed by a single main charge pump circuit, boosting time is distributed, and a boosting timing is optimized, thereby reducing variation in voltage and complying with high speed.
A semiconductor integrated circuit according to embodiment 1 of the present invention, which includes a function block and a boosting power circuit used in the function block, is characterized in that the boosting power circuit has a plurality of boosting circuits operating in synchronization with a signal for controlling the operation of the function block and a timing control circuit for producing a control signal of the plurality of boosting circuits in response to the signal for controlling the operation of the function block, the timing control circuit distributing the operations of the plurality of boosting circuits.
A semiconductor integrated circuit according to embodiment 2 of the present invention, which includes a memory block and a boosting power circuit used in the memory block, is characterized in that the boosting power circuit has a plurality of boosting circuits operating in synchronization with a signal for controlling the operation of the memory block and a timing control circuit for producing a control signal of the plurality of boosting circuits in response to the signal for controlling the operation of the memory block. The timing control circuit produces a first control signal, which is inverted after first delay time elapses at a timing of inactivating a memory activation signal, relative to a timing of activating the memory activation signal, and a second control signal operating after second delay time elapses relative to the first control signal, and the timing control circuit similarly produces a plurality of control signals for controlling the plurality of boosting circuits. The plurality of control signals distributes the operations of the plurality of boosting circuits.
A semiconductor integrated circuit according to embodiment 3 of the present invention includes a plurality of boosting circuits operating in synchronization with a memory activation signal, an auxiliary boosting circuit operating asynchronously to a memory activation signal with smaller capability of supplying electric charge than that of the boosting circuit, a timing control circuit for producing a control signal of the plurality of boosting circuits in response to a memory activation signal, an oscillator performing self-induced oscillation for the auxiliary boosting circuit, and a detection circuit for detecting a potential of boosting power source and controlling the operations of the timing control circuit and the oscillator, the timing control circuit distributing the operations of the plurality of boosting circuits, the boosting circuit including a charge pump circuit and a control signal producing circuit for producing a control signal of the charge pump circuit, the charge pump circuit including a electric charge transfer gate, first boosting means for doubling source voltage relative to the source voltage, and second boosting means for tripling the source voltage relative to the source voltage and the first boosted potential, the electric charge transfer gate having a source electrode connected to an output terminal and a drain electrode connected to the first boosted potential, the second boosted potential being connected to a gate electrode of the electric charge transfer gate so as to supply the first boosted potential to the output terminal.
A semiconductor integrated circuit according to embodiment 4 of the present invention includes a plurality of boosting circuits operating in synchronization with a memory activation signal, an auxiliary boosting circuit operating asynchronously to a memory activation signal with smaller capability of supplying electric charge than that of the boosting circuit, a timing control circuit for producing a control signal for the plurality of boosting circuits in response to a memory activation signal, an oscillator performing self-induced oscillation for the auxiliary boosting circuit, and a detection circuit for detecting a potential of boosted power source and controlling the operations of the timing control circuit and the oscillator, the timing control circuit distributing the operations of the plurality of boosting circuits, the boosting circuit including a charge pump circuit and a control signal producing circuit for producing a control signal of the charge pump circuit, the charge pump circuit including a electric charge transfer gate, first boosting means for doubling source voltage relative to the source voltage, and second boosting means for tripling the source voltage relative to the source voltage and the first boosted potential, (nxe2x88x921)th boosting means for boosting the source voltage by n times relative to the source voltage and (nxe2x88x921)-time boosted potential of the source voltage, and nth boosting means for boosting the source voltage by (n+1) times relative to the (nxe2x88x921)th boosted potential and the first boosted potential, the electric charge transfer gate having a source electrode connected to an output terminal and a drain electrode connected to the (nxe2x88x921)th boosted potential, the nth boosted potential being connected to a gate electrode of the electric charge transfer gate so as to supply the (nxe2x88x921)th boosted potential to the output terminal.
The semiconductor integrated circuit described in embodiment 5 of the present invention, according to embodiment 4, is characterized in that the charge pump circuit can be controlled by the same control signal, which is generated in the control signal producing circuit for controlling the charge pump circuit, regardless of a boosting multiple of the charge pump circuit.
A semiconductor integrated circuit according to embodiment 6 of the present invention includes a plurality of boosting circuits operating in synchronization with a memory activation signal, an auxiliary boosting circuit operating asynchronously to a memory activation signal with smaller capability of supplying electric charge than that of the boosting circuit, a timing control circuit for producing a control signal for the plurality of boosting circuits in response to a memory activation signal, an oscillator performing self-induced oscillation for the auxiliary boosting circuit, and a detection circuit for detecting a potential of boosted power source and controlling the operations of the timing control circuit and the oscillator, the timing control circuit distributing the operations of the plurality of boosting circuits, the detection circuit including a voltage drop circuit for reducing a voltage of a boosted potential by a constant current operation, a constant voltage generating circuit for generating constant voltage by a current mirror circuit, and first comparing means, the first comparing means comparing magnitudes of a reference potential generated by the constant voltage generating circuit and an output potential of the voltage drop circuit.
A semiconductor integrated circuit described in embodiment 7 of the present invention, according to embodiment 6, is characterized in that the first comparing means is configured by three differential amplifiers, a voltage drop potential generated from a boosted voltage in the voltage drop circuit is inputted to one of the inputs of a first differential amplifier, a constant voltage generated in the constant voltage circuit is inputted to the other input, the constant voltage is inputted to one of the inputs of a second differential amplifier, the voltage drop potential generated in the voltage drop circuit is inputted to the other input, an output signal of the first differential amplifier is used as one of the inputs of the third differential amplifier, and an output signal of the second differential amplifier is used as the other input, so that slight variation in voltage can be detected at high speed.
A semiconductor integrated circuit described in embodiment 8 of the present invention, according to embodiment 6, is characterized in that the detection circuit includes a voltage measuring terminal, second comparing means, a P-channel transistor, and an N-channel transistor, the second comparing means having the constant voltage connected to one of the inputs of the second comparing means and the voltage measuring terminal connected to the other input of the second comparing means, the P-channel transistor having a gate electrode connected to an output of the second comparing means, a drain electrode connected to a source potential, and a source electrode connected to the voltage measuring terminal, the N-channel transistor having a gate electrode connected to source potential, a source electrode connected to the voltage measuring terminal, and a drain electrode connected to a ground potential, a potential equal to that of the constant voltage, which is generated in the constant voltage circuit, is outputted to the voltage measuring terminal so as to measure the constant voltage.
A semiconductor integrated circuit described in embodiment 9 of the present invention, according to embodiment 6, is characterized in that the voltage drop circuit included in the detection circuit is provided with a voltage conversion circuit for converting source voltage to boosted source potential, a switch configured by a P-channel transistor and an N-channel transistor, and a second voltage drop circuit being activated only when the switch is turned on, an inverted signal of the state deciding signal has amplitude which is made equal to a boosted source potential via the voltage conversion circuit, the potential is applied to a gate potential of the P-channel transistor switch, and the state deciding signal is applied to a gate potential of the N-channel transistor switch, so that the state deciding signal changes output current applied to the voltage drop circuit, thereby achieving a high-speed operation.
A semiconductor integrated circuit described in embodiment 10 of the present invention, according to embodiment 6, is characterized in that the comparing means includes a differential amplifier having two driving transistors, constant voltage generated in the constant voltage circuit is applied to a gate electrode of one of the driving transistors and a state deciding signal is applied to a gate electrode of the other driving transistor, so that the state deciding signal changes responding speed of the differential amplifier, thereby changing an operating speed.
A semiconductor integrated circuit described in embodiment 11 of the present invention, according to embodiment 6, is characterized in that the detection circuit includes a plurality of test mode control signals as inputs, and a deciding output of the detection circuit or a first test mode control signal of the plurality of test mode control signals permits the boosting circuit to always be operated regardless of boosted potential.
A semiconductor integrated circuit described in embodiment 12 of the present invention, according to embodiment 6, is characterized in that the detection circuit includes an test mode in which a second test mode control signal of the plurality of test mode control signals activates the second comparative operator so as to measure the constant voltage from the voltage measuring terminal.
A semiconductor integrated circuit described in embodiment 13 of the present invention, according to embodiment 3, is characterized in that the control signal generating circuit for controlling the charge pump circuit includes an test mode in which an inverted logical sum is obtained on an input signal of the control signal producing circuit and a third test mode control signal of the plurality of test mode control signals so as to suspend the charge pump circuit.
A semiconductor integrated circuit described in embodiment 14 of the present invention, according to embodiment 9 or 10, is characterized in that the timing control circuit produces a state deciding signal for deciding whether a memory is activated or inactivated, the state deciding signal is activated according to an activating timing of the memory activation signal and is inactivated after predetermined delay time elapses from a timing of inactivating the memory activation signal.
As earlier mentioned, with the configuration of the semiconductor integrated circuit according to the present invention:
(1) The plurality of boosting circuits permits a boosting operation in synchronization with a consuming timing, and it is possible to suppress variation of a boosted potential VPP as compared with a boosting power circuit using a single boosting circuit.
(2) The charge pump circuit used as a boosting circuit has a capability limit of 2VDD and an operation can be performed with a sufficient margin even in the case of a lower source voltage VDD. Further, the charge pump circuit can be readily expanded to a triple or quadruple boosting circuit, and it is possible to use the same control signal as that of a double boosting circuit.
(3) Since the detection circuit is characterized by the absence of dependence on source voltage, an overboosting preventing circuit is not necessary even when source voltage is high.
(4) operating time of the boosting circuit is distributed so as to provide sufficient time for transferring electric charge per charge pump circuit. For this reason, it is possible to improve efficiency of the circuit as a whole.
(5) Since boosting is distributed, variation of the boosted source voltage VPP is reduced. Hence, as compared with a boosting power circuit using a single boosting circuit, a smoothing capacitor can be reduced so as to achieve small layout size.